W155
| Model | W155 |
| Description | Spread Spectrum Frequency Timing Generator |
| PDF file | Total 6 pages (File size: 90K) |
| Chip Manufacturer | CYPRESS |
W155
Functional Description
I/O Pin Operation
Pin 14 is a dual purpose l/O pin.
Upon power-up each I/O pin acts as a logic input, allowing the
determination of assigned device functions. A short time after
power-up, the logic state of each pin is latched and each pin
then becomes a clock output. This feature reduces device pin
count by combining clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
each l/O pin and ground or V
DD
. Connection to ground sets a
“0” bit, connection to V
DD
sets a “1” bit. See
Figure 1.
Upon W155 power-up, the first 2 ms of operation is used for
input logic selection. During this period, each clock output buff-
er is three-stated, allowing the output strapping resistor on
each l/O pin to pull the pin and its associated capacitive clock
load to either a logic HIGH or LOW state. At the end of the
2-ms period, the established logic 0 or 1 condition of each l/O
pin is then latched. Next the output buffer is enabled converting
all l/O pins into operating clock outputs. The 2-ms timer starts
when V
DD
reaches 2.0V. The input bits can only be reset by
turning V
DD
off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock outputs is <40Ω (nominal) which is minimally
affected by the 10-kΩ strap to ground or V
DD
. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length to
prevent system noise coupling during input logic sampling.
When each clock output is enabled following the 2-ms input
period, target (normal) output frequency is delivered assuming
that V
DD
has stabilized. If V
DD
has not yet reached full value,
output frequency initially may be below target but will increase
to target once V
DD
voltage has stabilized. In either case, a
short output clock cycle may be produced from the CPU clock
outputs when the outputs are enabled.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serial terminated clock
lines. The device outputs are CMOS-type which provide
rail-to-rail output swing.
Crystal Oscillator
The device requires one input reference clock to synthesize all
output frequencies. The reference clock can be either an ex-
ternally generated clock signal or the clock generated by the
internal crystal oscillator. When using an external clock signal,
pin X1 is used as the clock input and pin X2 is left open. The
input threshold voltage of pin X1 is (V
DD
)/2.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The device incor-
porates the necessary feedback resistor and crystal load ca-
pacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 20 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
20 pF should be used. This will typically yield reference fre-
quency accuracies within ±100 ppm. To achieve similar accu-
racies with a crystal calling for a greater load, external capac-
itors must be added such that the total load (internal, external,
and parasitic capacitors) equals that called for by the crystal.
Jumper Options
V
DD
10 kΩ
W155
Output
Buffer
Power-on
Reset
Timer
Output Three-state
Hold
Output
Low
D
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
Q
Data
Latch
Figure 1. Input Logic Selection Through Jumper Option
3
