W182-5
| Model | W182-5 |
| Description | Full Feature Peak Reducing EMI Solution |
| PDF file | Total 8 pages (File size: 128K) |
| Chip Manufacturer | CYPRESS |
W182
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in
Figure 4
should be used.
V
DD
decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V
DD
pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
DD
connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5
shows a recommended a 2-layer board layout.
Xtal Connection or Reference Input
Xtal Connection or NC
GND
1
2
3
4
5
6
7
W182
14
13
12
11
10
9
8
R1
Clock
Output
C1
0.1 µF
C3
0.1µF
3.3V or 5V System Supply
FB
C2
10 µF Tantalum
Figure 4. Recommended Circuit Configuration
C1, C3 = High-frequency supply decoupling
capacitor (0.1-µF recommended).
C2 = Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
R1 = Match value to line impedance
Xtal Connection or Reference Input
Xtal Connection or
NC
FB
= Ferrite Bead
= Via T GND Plane
o
G
G
C3
G
C1
G
G
Clock Output
R1
G
Power Supply Input
(3.3V or 5V)
FB
C2
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
W182
W182-5
Document #: 38-00789-A
Package
Name
G
Package Type
14-Pin Plastic SOIC (150-mil)
7
