W184-5
| Model | W184-5 |
| Description | Six Output Peak Reducing EMI Solution |
| PDF file | Total 8 pages (File size: 131K) |
| Chip Manufacturer | CYPRESS |
W184
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in
Figure 4
should be used.
V
DD
decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V
DD
pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
DD
connection can be
made via a ferrite bead, as shown.
Clock Output
R1
1
Logic Input
Reference Input
24
23
22
21
20
19
18
17
16
15
14
13
W184
Logic Input
Logic Input
Logic Input
C1
0.1 µF
2
3
4
5
6
7
8
9
10
11
12
XTAL connection or NC
Logic Input
Logic Input
Clock Output
Clock Output
Clock Output
R1
R1
R1
NC
Logic Input
R1
R1
Clock Output
R1
Clock Output
Clock Output
C1
0.1 µF
C1
0.1 µF
C1
0.1 µF
3.3 or 5V System Supply
FB
C2
10-µF Tantalum
Figure 4. Recommended Circuit Configuration
Ordering Information
Ordering Code
W184
W184-5
Document #: 38-00797-B
Package
Name
H
Package Type
24-Pin SSOP (209-mil)
7
