W195B
| Model | W195B |
| Description | Frequency Generator for Integrated Core Logic |
| PDF file | Total 13 pages (File size: 144K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
W195B
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clocks
• Nine copies of SDRAM clocks
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Two copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
• Power-down control
• I
2
C interface for turning off unused clocks
SDRAM, APIC, 48MHz Output Skew: ........................ 250 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@100 MHz): ..................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: ....................................................± 0.5 ns
Table 1. Frequency Selections
FS3 FS2 FS1 FS0 CPU SDRAM 3V66
1
1
1
1 133.6 133.6
66.8
1
1
1
0
Reserved
1
1
0
1 100.2 100.2
66.8
1
1
0
0
66.8
100.2
66.8
1
0
1
1
105
105
70
1
0
1
0
110
110
73.3
1
0
0
1
114
114
76
1
0
0
0
119
119
79.3
0
1
1
1
124
124
82.7
0
1
1
0
129
129
64.5
0
1
0
1
95
95
63.3
0
1
0
0
138
138
69
0
0
1
1
150
150
75
0
0
1
0
75
113
75
0
0
0
1
90
90
60
0
0
0
0
83.3
125
83.3
PCI APIC
33.4 16.7
33.4
33.4
35
36.7
38
39.7
41.3
32.3
31.7
34.5
37.5
37.5
30
41.7
16.7
16.7
17.5
18.3
19
19.8
20.7
16.1
15.8
17.3
18.8
18.8
15
20.8
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: .................................................. 500 ps
CPU, 3V66 Output Skew: ........................................... 175 ps
Block Diagram
VDDQ3
Pin Configuration
REF2x/FS3*
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
GND
FS0*/PCI0
FS1^/PCI1
FS2*/PCI2
GND
PCI3
PCI4
VDDQ3
PCI5
PCI6
PCI7
GND
48MHz_0
48MHz_1
SI0/24_48#MHz*
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
[1]
X1
X2
XTAL
OSC
PLL REF FREQ
REF2X/FS3*
VDDQ2
SDATA
SCLK
FS3*
FS2*
FS1*
FS0*
I
2
C
Logic
Divider,
Delay,
and
Phase
Control
Logic
2
CPU0:1
APIC
VDDQ3
3V66_0:1
PCI0/FS0*
PCI1/FS1*
PCI2/FS2*
5
9
2
PLL 1
PCI3:7
SDRAM0:8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
APIC
VDDQ2
CPU0
CPU1
GND
VDDQ3
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
SDRAM8
GND
PWRDWN#*
SCLK
VDDQ3
GND
SDATA
PWRDWN#
PLL2
/2
2
VDDQ3
48MHz_0:1
SI0/24_48#MHz*
Note:
1. Internal 250K pull-up or pull down resistors present on inputs
marked with * or ^ respectively. Design should not rely solely on
internal pull-up or pull down resistor to set I/O pins HIGH or LOW
respectively.
W195B
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
October 13, 1999, rev. **
