W211B
| Model | W211B |
| Description | FTG for 440BX, VIA Apollo Pro-133, and ProMedia |
| PDF file | Total 16 pages (File size: 177K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
W211B
FTG for 440BX, VIA Apollo Pro-133, and ProMedia
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Single-chip system frequency synthesizer for 440BX,
VIA Apollo Pro-133, and ProMedia
• Supports Intel® Pentium® II and Cyrix class processors
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 200 MHz
• SMBus interface for programming
• Power management control inputs
• Available in 48-pin SSOP
• SDRAM Range = 66 MHz to 133 MHz
SDRAMIN to SDRAM0:12 Delay:........................4.5 – 6.0 ns
Table 1. Mode Input Table
Mode
Pin 2
0
CPU_STOP#
1
REF0
Table 2. Pin Selectable Frequency
Input Address
CPU_F,
PCI_F,
Spread
FS3 FS2 FS1 FS0 CPU1 (MHz) 1:5 (MHz) Spectrum
1
1
1
1
133.3
33.3
±0.5%
1
1
1
0
75
37.5
OFF
1
1
0
1
100.2
33.3
±0.5%
1
1
0
0
66.8
33.4
±0.5%
1
0
1
1
79
39.5
OFF
1
0
1
0
110
36.7
OFF
1
0
0
1
115
38.3
OFF
1
0
0
0
120
30
OFF
0
1
1
1
133.3
33.3
–0.5%
0
1
1
0
83
27.7
OFF
0
1
0
1
100.2
33.3
–0.5%
0
1
0
0
66.8
33.4
–0.5%
0
0
1
1
122
30.5
–0.5%
0
0
1
0
129
32.3
OFF
0
0
0
1
138
34.5
OFF
0
0
0
0
95
31.7
–0.5%
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DDQ3
: .................................................................... 3.3V±5%
V
DDQ2
: .................................................................... 2.5V±5%
Block Diagram
X1
X2
XTAL
OSC
VDDQ3
REF0/(CPU_STOP#)
REF1/FS0
Pin Configuration
[1]
VDDQ3
REF0/(CPU_STOP#)
GND
X1
X2
VDDQ3
PCI0/MODE
PCI1/FS1*
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SMBus SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
IOAPIC
REF1/FS0*
GND
CPU_F
CPU1
VDDQ2
PWRDWN#
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS2*
24_48MHz/FS3^
PLL Ref Freq
I/O Pin
Control
PWRDWN#
CPU_F
Stop
Clock
Control
÷2,3,4
W211B
CPU1
PLL 1
VDDQ3
PCI0/MODE
PCI1/FS1
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS2
÷2
SDATA
SCLK
SMBus
Logic
PLL2
{
SDRAMIN
13
24_48MHz/FS3
VDDQ3
SDRAM0:12
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07174 Rev. **
•
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•
San Jose
•
CA 95134 • 408-943-2600
Revised September 25, 2001
