W27C520W-90
| Model | W27C520W-90 |
| Description | 64K X 8 ELECTRICALLY ERASABLE EPROM |
| PDF file | Total 16 pages (File size: 238K) |
| Chip Manufacturer | WINBOND |
Preliminary W27C520
64K
×
8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27C520 is a high speed, low power Electrically Erasable and Programmable Read Only Memory
organized as 65,536
×
8 bits. It includes latches for the lower 8 address lines to multiplex with the 8
data lines. To cooperate with the MCU, this device could save the external TTL component, also cost
and space. It requires only one supply in the range of 3.0V to 3.6V or 4.5V to 5.5V in normal read
mode. The W27C520 provides an electrical chip erase function. It will be a great convenient when you
need to change/update the contents in the device.
FEATURES
•
High speed access time: 70/90 nS (max.)
•
Read operating current: 8/20 mA (max.)
•
Erase/Programming operating current
•
High Reliability CMOS Technology
−
2K V ESD Protection
−
200 mA Latchup Immunity
•
Fully static operation
•
All inputs and outputs directly LVTTL/CMOS
30 mA (max.)
•
Standby current: 20/100
µA
(max.)
•
Unregulated battery power supply range,
3.0V to 3.6V and 4.5V to 5.5V
•
+13V erase and programming voltage
compatible
•
Three-state outputs
•
Available p
ackages: 20-pin TSSOP and 20-pin
SOP
PIN CONFIGURATIONS
A10
A12
A14
ALE
V
DD
OE/VPP
A15
A13
A11
A9
1
2
3
4
5
6
7
8
9
10
20
19
18
17
BLOCK DIAGRAM
A8
AD1
AD3
AD5
AD7
GND
AD6
AD4
AD2
AD0
A15 - A8
V
DD
GND
AD7 - AD0
L
A
T
C
H
E
S
ALE
OE / V
PP
CONTROL
OUTPUT
BUFFER
TSSOP
16
Top View
15
14
13
12
DECODER
MEMORY
ARRAY
11
OE/VPP
A15
A13
A11
A9
AD0
AD2
AD4
AD6
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
VDD
ALE
A14
A12
A10
A8
AD1
AD3
AD5
AD7
PIN DESCRIPTION
SYMBOL
AD0−AD7
A8−A15
ALE
OE /V
PP
V
DD
GND
DESCRIPTION
Address/Data Inputs/Outputs
Address Inputs
Address Latch Enable
Output Enable, Program/Erase
Supply Voltage
Power Supply
Ground
SOP
16
Top View
15
14
13
12
11
-1-
Publication Release Date: October 2000
Revision A1
