W27E512Q-70
| Model | W27E512Q-70 |
| Description | 64K X 8 ELECTRICALLY ERASABLE EPROM |
| PDF file | Total 16 pages (File size: 192K) |
| Chip Manufacturer | WINBOND |
W27E512
64K
×
8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27E512 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65536
×
8 bits that operates on a single 5 volt power supply. The W27E512
provides an electrical chip erase function.
FEATURES
•
High speed access time:
•
•
•
•
45/55/70/90/120/150 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current
30 mA (max.)
Standby current: 1 mA (max.)
Single 5V power supply
•
+14V erase/+12V programming voltage
•
Fully static operation
•
All inputs and outputs directly TTL/CMOS
compatible
•
Three-state outputs
•
Available p
ackages: 28-pin 600 mil DIP, 330 mil
SOP, TSOP and 32-pin PLCC
PIN CONFIGURATIONS
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin
DIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A14
A13
A8
A9
A11
OE/Vpp
A10
CE
Q7
Q6
Q5
Q4
Q3
BLOCK DIAGRAM
OUTPUT
BUFFER
Q0
.
.
Q7
CE
OE/V
PP
CONTROL
A0
.
DECODER
.
A15
CORE
ARRAY
A A
V A A
A 1 1 N C 1 1
7 2 5 C C 4 3
4 3 2 1 3 3 3
2 1 0 29
5
28
6
27
7
26
8
32-pin
25
PLCC
9
24
10
23
11
12 1 1 1 1 1 1 2 22
13 4 5 6 7 8 9 0 21
Q Q G N Q Q Q
1 2 N C 3 4 5
D
OE/Vpp
A11
A9
A8
A13
A14
V
CC
A15
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
V
CC
GND
A8
A9
A11
NC
OE/Vpp
A10
CE
Q7
Q6
A6
A5
A4
A3
A2
A1
A0
NC
Q0
PIN DESCRIPTION
SYMBOL
A0−A15
Q0−Q7
CE
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable, Program/Erase
Supply Voltage
Power Supply
Ground
No Connection
OE /V
PP
V
CC
GND
NC
28-pin
TSOP
-1-
Publication Release Date: June 2000
Revision A9
