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Home > Data Sheet > W39V040ATZ
W39V040ATZ

W39V040ATZ

Model W39V040ATZ
Description Flash, 512KX8, 11ns, PDSO40, LEAD FREE, 10 X 20 MM, TSOP-40
PDF file Total 39 pages (File size: 440K)
Chip Manufacturer WINBOND
Download (440K)

W39V040A Data Sheet
512K
×
8 CMOS FLASH MEMORY
WITH LPC INTERFACE
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PIN CONFIGURATIONS............................................................................................................. 4
BLOCK DIAGRAM ...................................................................................................................... 5
PIN DESCRIPTION..................................................................................................................... 5
FUNCTIONAL DESCRIPTION.................................................................................................... 6
6.1
Interface Mode Selection and Description...................................................................... 6
6.2
Read (Write) Mode ......................................................................................................... 6
6.3
Reset Operation.............................................................................................................. 6
6.4
Boot Block Operation and Hardware Protection at Initial - #TBL and #WP.................... 6
6.5
Chip Erase Operation ..................................................................................................... 7
6.6
Sector/Page Erase Operation......................................................................................... 7
6.7
Program Operation ......................................................................................................... 7
6.8
Hardware Data Protection .............................................................................................. 8
6.9
Data Polling (DQ7)- Write Status Detection ................................................................... 8
6.10 Toggle Bit (DQ6)- Write Status Detection....................................................................... 8
6.11 Multi-Chip Operation....................................................................................................... 8
6.12 Register........................................................................................................................... 8
6.12.1
6.12.2
General Purpose Inputs Register .................................................................................8
Product Identification Registers ....................................................................................9
6.13
6.14
Memory Address Map..................................................................................................... 9
Table of Operating Modes ............................................................................................ 10
6.14.1
6.14.2
6.14.3
Operating Mode Selection - Programmer Mode .........................................................10
Operating Mode Selection - LPC Mode ......................................................................10
Standard LPC Memory Cycle Definition .....................................................................11
7.
6.15 Table of Command Definition ....................................................................................... 11
6.16 Embedded Programming Algorithm.............................................................................. 13
6.17 Embedded Erase Algorithm.......................................................................................... 14
6.18 Embedded #Data Polling Algorithm.............................................................................. 15
6.19 Embedded Toggle Bit Algorithm ................................................................................... 15
6.20 Software Product Identification and Boot Block Lockout Detection Acquisition Flow .. 16
6.21 Boot Block Lockout Enable Acquisition Flow................................................................ 17
DC CHARACTERISTICS .......................................................................................................... 18
7.1
Absolute Maximum Ratings .......................................................................................... 18
7.2
Programmer Interface Mode DC Operating Characteristics......................................... 18
7.3
LPC Interface Mode DC Operating Characteristics...................................................... 19
7.4
Power-up Timing........................................................................................................... 19
7.5
Capacitance .................................................................................................................. 19
Publication Release Date: June 21, 2005
Revision A6
-1-
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