W3E32M64S-250B3M
| Model | W3E32M64S-250B3M |
| Description | DDR DRAM, 32MX64, 0.8ns, CMOS, PBGA208, BGA-208 |
| PDF file | Total 16 pages (File size: 1001K) |
| Chip Manufacturer | MERCURY |
W3E32M64S-XB3X
256 – 32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266, 333**
Package:
• 208 Plastic Ball Grid Array (PBGA), 13 x 22mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR) architecture; two
data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received with
data, i.e., source-synchronous data capture (one per byte)
DQS edge-aligned with data for READs; center-aligned with
data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data (one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature Ranges
Organized as 32M x 64
• Can be user organized as 2x32Mx32 or 4x32Mx16
Weight: W3E32M64S-XB3X — 1.5 grams typical
BENEFITS
73% Space Savings vs. FPBGA
• 43% Space Savings vs TSOP
Reduced part count
21% I/O reduction vs TSOP
• 13% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 64M x 64 density (contact factory for
information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic
random-access, memory using 4 chips containing 536,870,912 bits.
Each chip is internally configured as a quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate architecture to
achieve high-speed operation. The double data rate architecture is
essentially a 2n-prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins. A single read
or write access for the 256MB DDR SDRAM effectively consists of
a single 2n-bit wide, one-clock-cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted externally, along
with data, for use in data capture at the receiver strobe transmitted
by the DDR SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for READs and
center-aligned with data for WRITEs. Each chip has two data
strobes, one for the lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock (CK
and CK#); the crossing of CK going HIGH and CK going LOW will
be referred to as the positive edge of CK. Commands (address
and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE
burst lengths of 2, 4, or 8 locations. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated
at the end of the burst access.
* This product is subject to change without notice.
**
For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature CL = 3.
Microsemi Corporation reserves the right to change products or specifications without notice.
January 2014
Rev. 0
© 2014 Microsemi Corporation. All rights reserved.
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Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
