W3EG6466S262AD4G
| Model | W3EG6466S262AD4G |
| Description | DRAM, |
| PDF file | Total 13 pages (File size: 194K) |
| Chip Manufacturer | WEDC |
White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY*
512MB – 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
DDR200, DDR266 and DDR333
• JEDEC design specifications
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.5mm (1.38")
BD4: 31.75mm (1.25")
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The W3EG6466S is a 2x32Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of sixteen 32Mx8
components as eight 64Mx8 stacked DDR SDRAMs
in 66 pin TSOP packages mounted on a 200 pin FR4
substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
