W3H128M72ER-533SBC
| Model | W3H128M72ER-533SBC |
| Description | DDR DRAM, 128MX72, 0.5ns, CMOS, PBGA255, 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255 |
| PDF file | Total 30 pages (File size: 1M) |
| Chip Manufacturer | MERCURY |
W3H128M72ER-XNBX
ADVANCED*
128M x 72 REGISTERED DDR2 SDRAM 255 PBGA
FEATURES
Data rate = 667, 533, 400 Mb/s
Package:
• 255 Plastic Ball Grid Array (PBGA), 23 x 21mm
2
• 1.27mm pitch
Core Supply Voltage = 1.8V
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with clock
signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 4, 5 or 6
CK/CK# Termination options available
• 0 ohm, 20 ohm
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* t
CK
Commercial, Industrial and Military Temperature Ranges
1GByte Organized as 128M x 72
Weight: W3H128M72ER-XNBX - 4 grams max
* This product is under development, is not fully qualified or characterized and is subject to
change or cancellation without notice.
BENEFITS
45% Space savings vs. FBGA
Reduced part count
51% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
W3H128M72ER-XNBX
5.5
11.5
11.5
11.5
11.5
11.5
21
13.5
96
FBGA
14.0
84
FBGA
84
FBGA
84
FBGA
84
FBGA
84
FBGA
W3H32M64EA-XSBX
23
S
A
V
I
N
G
S
45%
51%
Area
I/O Count
5 x 161mm
2
+ 1 x 74mm
2
= 879mm
2
5 x 84 balls + 1 x 96 balls = 516 balls
483mm
2
255 Balls
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011
Rev. 8
© 2011 Microsemi Corporation. All rights reserved.
1
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