W3H32M64EA-533SBM
Model | W3H32M64EA-533SBM |
Description | DDR DRAM, 32MX64, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
PDF file | Total 27 pages (File size: 1M) |
Chip Manufacturer | MERCURY |
W3H32M64EA-XSBX
ADVANCED*
256MB – 32M x 64 DDR2 SDRAM Single-Rank 208 PBGA MCP
FEATURES
Data rate = 667, 533, 400 Mb/s
Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 20mm
• 1.0mm pitch
Supply Voltage = 1.8V ± 0.1V
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with clock
signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 3, 4 or 5
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* t
CK
Commercial, Industrial and Military Temperature Ranges
Organized as 32M x 64
Weight: W3H32M64EA-XSBX - 2.5 grams typical
BENEFITS
62% Space savings vs. FBGA
Reduced part count
42% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Upgradeable to 64M x 64 density (contact factory for
information)
*This product is under development, is not qualified or characterized and is subject to change or
cancellation without notice.
TYPICAL APPLICATION
RAM
Host
FPGA/
Processor
DDR2/DDR3
W3X128M72-XBI
SSD (SLC)
MSM32/MSM64 (SATA BGA)
W7N16GVHxxBI (PATA BGA)
n)
M512/M256/M128 (SATA, 2.5in)
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
11.0
11.0
11.0
11.0
W3H32M64EA-XSBX
19.0
90
FBGA
90
FBGA
90
FBGA
90
FBGA
W3H32M64EA-XSBX
20
16
S
A
V
I
N
G
S
62%
42%
Area
I/O Count
4 x 209mm
2
= 836mm
2
4 x 90 balls = 360 balls
320mm
2
208 Balls
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011
Rev.1
© 2011 Microsemi Corporation. All rights reserved.
1
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