W3HG128M72AEF665F1SAG
| Model | W3HG128M72AEF665F1SAG |
| Description | DDR DRAM Module, 256MX4, CMOS, ROHS COMPLIANT, FBDIMM-240 |
| PDF file | Total 17 pages (File size: 257K) |
| Chip Manufacturer | WEDC |
White Electronic Designs
W3HG128M72AEF-Fx
ADVANCED*
1GB – 128Mx72 DDR2 SDRAM FBDIMM, ECC
FEATURES
240-pin DDR2 fully buffered, dual in-line memory
module (FBDIMM) with ECC to detect and report
channel errors to the host memory controller.
Fast DDR2 DRAM data transfer rates: PC2-6400*,
PC2-5300, and PC2-4300
3.2 Gb/s and 4.0 Gb link transfer rates
High speed differential point-to-point link between
host memory controller and the AMB using serial,
dual-simplex bit lanes
• 10-pair southbound (data path to FBDIMM)
• 14-pair northbound (data path to FBDIMM)
Fault tolerant; can work around a bad bit lane in
each direction
High density scaling with up to 8 dual-rank modules
(288 DDR2 SDRAM devices) per channel
SMBus interface to AMB for configuration register
access.
In-band and out-bank command access
Deterministic protocol
• Enables memory controller to optimize DRAM
access for maximum performance
• Delivers precise control and repeatable memory
behavior
Automatic DDR2 SDRAM bus and channel
calibration
Transmitter de-emphasis to reduce ISI
MBIST and IBIST test functions
Transparent mode for DDR2 SDRAM test support
V
CC
= V
CCQ
= +1.8V for DDR2 SDRAM
V
REF
= 0.9V SDRAM C/A termination
V
CC
= 1.5V for advanced memory buffer (AMB)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual rank
RoHS
DESCRIPTION
The W3HG128M72AEF is a 128Mx72 fully buffered 240-
pin Double Data Rate 2 SDRAM memory module based
on 512Mb DDR2 SDRAM components. The module
consists of eighteen 128Mx4, in FBGA package and a
AMB mounted on a 240 pin FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
PERFORMANCE PARAMETERS
Speed Grade
665
534
Module Bandwidth
PC2-5300
PC2-4200
Peak Channel Throughput
8.0 GB/s
6.4 GB/s
Link Transfer Rate
4.0 GT/s
3.2 GT/s
Latency (CL-t
RCD
-t
RP
)
5-5-5
4-4-4
* Consult factory for availability
Note: JEDEC has not yet adopted a
fi
nal FBDIMM standard
September 2007
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
