W48S87-04
| Model | W48S87-04 |
| Description | Spread Spectrum 3 DIMM Desktop Clock |
| PDF file | Total 21 pages (File size: 203K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
W48S87-04
Spread Spectrum 3 DIMM Desktop Clock
Features
• Outputs
— 4 CPU Clock (2.5V or 3.3V, 50 to 83.3 MHz)
— 7 PCI (3.3V)
— 1 48-MHz for USB (3.3V)
— 1 24-MHz for Super I/O (3.3V)
— 2 REF (3.3V)
— 1 IOAPIC (2.5V or 3.3V)
— 12 SDRAM
• Serial data interface provides additional frequency
selection, individual clock output disable, and other
functions
• Smooth transition supports dynamic frequency
assignment
• Frequency selection not affected during power
down/up cycle
• Supports a variety of power-saving options
• 3.3V operation
• Available in 48-pin SSOP (300 mils)
Key Specifications
±0.5% Spread Spectrum Modulation: ......................... ±0.5%
Jitter (Cycle-to-Cycle): .................................................250 ps
Duty Cycle: ................................................................ 45-55%
CPU-PCI Skew: ........................................................ 1 to 4 ns
PCI-PCI or CPU-CPU Skew: .......................................250 ps
Table 1. Pin Selectable Frequency
[1]
Input Address
FS2
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
CPU, SDRAM
Clocks (MHz)
50.0
75.0
83.3
68.5
55.0
75.0
60.0
66.8
PCI Clocks
(MHz)
25.0
32.0
41.65
34.25
27.5
37.5
30.0
33.4
Block Diagram
SDATA
SCLOCK
Serial Port
Device
Control
PLL Ref
Freq
X1
X2
CPU3.3#_2.5
FS0
FS1
FS2
XTAL OSC
CPU Clock
Mode Control
Freq
Select
I/O
MODE
VDDL1
IOAPIC
PLL1
VDDL2
Stop
Clock
Cntrl
CPU_STOP#
÷2
4
CPU0:3
VDD3
12
SDRAM0:11
VDD2
I/O
I/O
4
PCI_F/FS1
PCI0/FS2
PCI1:4
PCI5(PWR_DWN#)
VDD1
I/O
I/O
48MHZ/FS0
24MHZ/MODE
VDD1
REF0/CPU3.3#_2.5
REF1(CPU_STOP#)
Pin Configuration
[2]
VDD1
REF0/CPU3.3#_2.5
GND
X1
X2
VDD2
PCI_F/FS1
PCI0/FS2
GND
PCI1
PCI2
PCI3
PCI4
VDD2
PCI5(PWR_DWN#)
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL1
IOAPIC
REF1(CPU_STOP#)
GND
CPU0
CPU1
VDDL2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
GND
48MHZ/FS0
24MHZ/MODE
W48S87-04
PWR_DWN#
Power Down
Control
÷2
PLL2
÷4
MODE
Notes:
1. Additional frequency selections provided by serial data interface; refer to
Table 5
on page 10.
2. Signal names in parenthesis denotes function is selectable through mode pin register strapping.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
October 19, 1999, rev. **
