X1227S8IZ-4.5A
| Model | X1227S8IZ-4.5A |
| Description | 2-Wire RTC Real TimeClock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 28 pages (File size: 419K) |
| Chip Manufacturer | INTERSIL |
X1227
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
t
WC
Stop
Condition
Start
Condition
Power-up Timing
Symbol
t
PUR(1)
t
PUW(1)
Parameter
Time from Power-up to Read
Time from Power-up to Write
Min.
Typ.
(2)
Max.
1
5
Units
ms
ms
Notes: (1) Delays are measured from the time V
CC
is stable until the specified operation can be initiated. These parameters are periodically
sampled and not 100% tested.
(2) Typical values are for T
A
= 25°C and V
CC
= 5.0V
Nonvolatile Write Cycle Timing
Symbol
t
WC(1)
Parameter
Write Cycle Time
Min.
Typ.
(1)
5
Max.
10
Units
ms
Notes: (1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Watchdog/Low Voltage Reset Parameters
Symbols
V
PTRIP
Parameters
Programmed Reset Trip Voltage
X1227-4.5A
X1227
X1227-2.7A
X1227-2.7
V
CC
Detect to RESET LOW
Power-up Reset Time-out Delay
V
CC
Fall Time
V
CC
Rise Time
Watchdog Timer Period:
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
Watchdog Reset Time-out Delay
2-Wire interface
Reset Valid V
CC
Min.
4.5
4.25
2.7
2.55
100
10
10
1.7
725
225
225
1
1.0
Typ.
4.68
4.38
2.93
2.68
200
Max.
4.75
4.5
3.0
2.7
500
400
Unit
V
t
RPD
t
PURST
t
F
t
R
t
WDO
ns
ms
µs
µs
1.75
750
250
250
1.8
775
275
275
s
ms
ms
ms
µs
V
t
RST
t
RSP
V
RVALID
7
FN8099.1
September 15, 2005
