X1227S8Z-2.7A
| Model | X1227S8Z-2.7A |
| Description | 2-Wire RTC Real TimeClock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 28 pages (File size: 419K) |
| Chip Manufacturer | INTERSIL |
X1227
whether V
CC
or V
BACK
is applied first. The loss of only
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but must
have a zero in these bit positions. The Data Byte output
during a SR read will contain zeros in these bit locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
BP2
BP1
BP0
Protected Addresses
X1227
None (Default)
180
h
- 1FF
h
100
h
- 1FF
h
000
h
- 1FF
h
000
h
- 03F
h
000
h
- 07F
h
000
h
- 0FF
h
000
h
- 1FF
h
Watchdog Timer Control Bits—WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Table 4. Watchdog Timer Time-Out Options
WD1 WD0
0
0
1
1
0
1
0
1
Watchdog Time-Out Period
1.75 seconds
750 milliseconds
250 milliseconds
Disabled (default)
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
DTR Register
DTR2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Array Lock
None
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 pgs
DTR1
0
1
0
1
0
1
0
1
DTR0
0
0
1
1
0
0
1
1
Estimated frequency
PPM
0 (Default)
+10
+20
+30
0
-10
-20
-30
13
FN8099.1
September 15, 2005
