X1228S14IZ-2.7
| Model | X1228S14IZ-2.7 |
| Description | Real Time Clock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 29 pages (File size: 428K) |
| Chip Manufacturer | INTERSIL |
X1228
PIN DESCRIPTIONS
14 Ld TSSOP/SOIC
X1
X2
NC
NC
NC
RESET
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
V
BACK
PHZ/IRQ
NC
NC
SCL
SDA
NC = No internal connection
PIN ASSIGNMENTS
Pin Number
SOIC/TSSOP
1
Symbol
X1
Brief Description
X1.
The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended crystal
is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the placement of the crystal and the layout
of the circuit. Plenty of ground plane around the device and short traces to X1 are highly
recommended. See Application section for more recommendations.
X2.
The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended crystal
is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the placement of the crystal and the layout
of the circuit. Plenty of ground plane around the device and short traces to X2 are highly
recommended. See Application section for more recommendations.
RESET Output – RESET.
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has dropped below
a fixed V
TRIP
threshold. It is an open drain active LOW output. Recommended value for the
pullup resistor is 5kΩ. If unused, tie to ground.
V
SS
.
Serial Data (SDA).
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls the
fall time of the output signal with the use of a slope controlled pull-down. The circuit is
designed for 400kHz 2-wire interface speeds.
Serial Clock (SCL).
The SCL input is used to clock all data into and out of the device. The
input buffer on this pin is always active (not gated).
Programmable Frequency/Interrupt Output – PHZ/IRQ.
This is either an output from the
internal oscillator or an interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz
or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of the
Clock Control Memory map. See “Programmable Frequency Output Bits—FO1, FO0” on
page 14.
V
BACK
.
This input provides a backup supply voltage to the device. V
BACK
supplies power
to the device in the event the V
CC
supply fails. This pin can be connected to a battery, a
Supercap or tied to ground if not used.
V
CC
.
2
X2
6
RESET
7
8
V
SS
SDA
9
12
SCL
PHZ/IRQ
13
V
BACK
14
V
CC
3
FN8100.2
October 17, 2005
