X1228S14IZ-4.5A
| Model | X1228S14IZ-4.5A |
| Description | Real Time Clock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 29 pages (File size: 428K) |
| Chip Manufacturer | INTERSIL |
X1228
Figure 10. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Array
CCR
1
1
0
1
1
0
0
1
1
1
1
R/W
Slave Address Byte
Byte 0
Word Address 1
0
0
0
0
0
0
0
A8
Byte 1
A7
A6
A5
A4
A3
A2
A1
A0
Word Address 0
Byte 2
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
Byte 3
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1228 responds with
an acknowledge. After receiving both address bytes
Figure 11. Byte Write Sequence
Signals from
the Master
S
t
a
r
t
1
S
t
o
p
the X1228 awaits the eight bits of data. After receiving
the 8 data bits, the X1228 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1228 then
begins an internal write cycle of the data to the nonvol-
atile memory. During the internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 11.
Slave
Address
1 110
A
C
K
Word
Address 1
0000000
A
C
K
Word
Address 0
Data
SDA Bus
Signals From
The Slave
A
C
K
A
C
K
Figure 12. Writing
30
bytes to a
64-byte
memory page starting at address
40.
7 Bytes
23 Bytes
Address
=6
Address Pointer
Ends Here
Addr = 7
Address
40
Address
63
20
FN8100.2
October 17, 2005
