X1228S14Z-2.7
| Model | X1228S14Z-2.7 |
| Description | Real Time Clock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 29 pages (File size: 428K) |
| Chip Manufacturer | INTERSIL |
X1228
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
t
WC
Stop
Condition
Start
Condition
Power-up Timing
Symbol
t
PUR(1)
t
PUW(1)
Parameter
Time from Power-up to Read
Time from Power-up to Write
Min.
Typ.
(2)
Max.
1
5
Units
ms
ms
Notes: (1) Delays are measured from the time V
CC
is stable until the specified operation can be initiated. These parameters are not 100% tested.
V
CC
slew rate should be between 0.2mV/µsec and 50mV/µsec.
(2) Typical values are for T
A
= 25°C and V
CC
= 5.0V
Nonvolatile Write Cycle Timing
Symbol
t
WC(1)
Note:
Parameter
Write Cycle Time
Min.
Typ.
(1)
5
Max.
10
Units
ms
(1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Watchdog/Low Voltage Reset Parameters (SeeFigures 3 and 4)
Symbols
Parameters
Programmed Reset Trip Voltage
X1228-4.5A
X1228
X1228-2.7A
X1228-2.7
V
CC
Detect to RESET LOW
Power-up Reset Time-out Delay
V
CC
Fall Time
V
CC
Rise Time
Watchdog Timer Period (Crystal = 32.768kHz):
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
Watchdog Reset Time-out Delay (Crystal=32.768kHz)
2-Wire interface
Reset Valid V
CC
100
10
10
1.7
725
225
225
1
1.0
1.75
750
250
250
1.8
775
275
275
250
Min.
4.50
4.25
2.75
2.55
Typ.
4.63
4.38
2.85
2.65
Max.
4.75
4.50
2.95
2.75
500
400
Unit
V
PTRIP
V
t
RPD
t
PURST
t
F
t
R
t
WDO
ns
ms
µs
µs
s
ms
ms
ms
µs
V
t
RST
t
RSP
V
RVALID
7
FN8100.2
October 17, 2005
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 X1228S14Z-2.7A
|
Real Time Clock/Calendar/CPU Supervisor with EEPROM | INTERSIL | Preview |
|
X1228S14Z-2.7T1
|
Real Time Clock/Calendar/CPU Supervisor with EEPROM | INTERSIL | Preview |
