X1228S14Z-2.7A
| Model | X1228S14Z-2.7A |
| Description | Real Time Clock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 29 pages (File size: 428K) |
| Chip Manufacturer | INTERSIL |
X1228
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1.
2.
3.
4.
5.
Alarm 0 (8 bytes; non-volatile)
Alarm 1 (8 bytes; non-volatile)
Control (4 bytes; non-volatile)
Real Time Clock (8 bytes; volatile)
Status (1 byte; volatile)
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24 hour time selection bit. The enable
bits specify which registers to use in the comparison
between the Alarm and Real Time Registers. For
example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
7
6
5
4
3
2
1
0
(optional)
Range
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
Status
RTC
(SRAM)
Control
(EEPROM)
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
DTR
ATR
INT
BL
BAT
0
0
Y23
0
0
MIL
0
0
0
0
IM
BP2
AL1
0
0
Y22
0
0
0
M22
S22
0
0
AL1E
BP1
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
ATR5
AL0E
BP0
0
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
ATR4
FO1
WD1
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
FO0
WD0
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
x
0
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
x
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
x
0
19/20
0-6
0-99
1-12
1-31
0-23
0-59
0-59
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
18h
11
FN8100.2
October 17, 2005
Default
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