X1228S14Z-4.5A
| Model | X1228S14Z-4.5A |
| Description | Real Time Clock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 29 pages (File size: 428K) |
| Chip Manufacturer | INTERSIL |
X1228
LOW VOLTAGE RESET OPERATION
When a power failure occurs, and the voltage to the
part drops below a fixed v
TRIP
voltage, a reset pulse is
issued to the host microcontroller. The circuitry moni-
tors the V
CC
line with a voltage comparator which
senses a preset threshold voltage. Power-up and
power-down waveforms are shown in Figure 4. The
Low Voltage Reset circuit is to be designed so the
RESET signal is valid down to 1.0V.
Figure 3. Watchdog Restart/Time Out
t
RSP
t
RSP
<t
WDO
t
RSP
>t
WDO
t
RST
t
RSP
>t
WDO
t
RST
When the low voltage reset signal is active, the operation
of any in progress nonvolatile write cycle is unaffected,
allowing a nonvolatile write to continue as long as possi-
ble (down to the power-on reset voltage). The low volt-
age reset signal, when active, terminates in progress
communications to the device and prevents new com-
mands, to reduce the likelihood of data corruption.
SCL
SDA
RESET
Start
Stop Start
Note:
All inputs are ignored during the active reset period (t
RST
).
Figure 4. Power-on Reset and Low Voltage Reset
V
TRIP
V
CC
t
PURST
t
RPD
t
R
RESET
t
F
V
RVALID
t
PURST
V
CC
THRESHOLD RESET PROCEDURE
[OPTIONAL]
The X1228 is shipped with a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
is not exactly right, or if
higher precision is needed in the V
TRIP
value, the
X1228 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvol-
atile write control signal.
Setting the V
TRIP
Voltage
It is necessary to reset the trip point before setting the
new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold voltage to the V
CC
pin and tie the RESET pin
to the programming voltage V
P
. Then write data 00h to
address 01h. The stop bit following a valid write opera-
tion initiates the V
TRIP
programming sequence. Bring
RESET to V
CC
to complete the operation.
Note:
this
operation may take up to 10 milliseconds to complete
and also writes 00h to address 01h of the EEPROM
array.
16
FN8100.2
October 17, 2005
