X1286V14
| Model | X1286V14 |
| Description | Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286 |
| PDF file | Total 25 pages (File size: 362K) |
| Chip Manufacturer | INTERSIL |
X1286
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
*n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Reg
Name
SR
SSEC
DW
YR
MO
DT
HR
MN
SC
Control
(EEPROM)
DTR
ATR
INT
BL
Alarm1
(EEPROM)
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
EMO1
EDT1
EHR1
EMN1
ESC1
EDW1
0
0
0
0
A1M22
A1S22
0
0
A1D21
A1H21
A1M21
A1S21
0
7
BAT
SS23
0
Y23
0
0
MIL
0
0
0
0
IM
BP2
6
AL1
SS22
0
Y22
0
0
0
M22
S22
0
0
AL1E
BP1
5
AL0
SS21
0
Y21
0
D21
H21
M21
S21
0
ATR5
AL0E
BP0
4
0
SS20
0
Y20
G20
D20
H20
M20
S20
0
ATR4
FO1
WD1
0
A1G20
A1D20
A1H20
A1M20
A1S20
3
0
SS13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
FO0
WD0
0
A1G13
A1D13
A1H13
A1M13
A1S13
2
RWEL
SS12
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
1
WEL
SS11
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
(optional)
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
Type
Status
RTC
(SRAM)
Range
0-99
0-6
0-99
1-12
1-31
0-23
0-59
0-59
RTCF
SS10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
01h
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
00h
00h
00h
00h
20
20h
00h
00h
00h
00h
00h
00h
0-6
1-12
1-31
0-23
0-59
0-59
Read Only Read Only Read Only
Read Only Read Only Read Only
DY2
A1G12
A1D12
A1H12
A1M12
A1S12
DY1
A1G11
A1D11
A1H11
A1M11
A1S11
DY0
A1G10
A1D10
A1H10
A1M10
A1S10
Read-only - Default = 20h
Unused - Default = RTC Year value (No EEPROM) - Future expansion
10
FN8101.0
March 29, 2005
Default
Bit
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 X1286V14I
|
Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286 | INTERSIL | Preview |
|
X1286V14I-T1
|
1 TIMER(S), REAL TIME CLOCK, PDSO14, 4.40 MM, PLASTIC, TSSOP-14 | RENESAS | Preview |
|
X1286V14ZT1
|
1 TIMER(S), REAL TIME CLOCK, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-14 | RENESAS | Preview |
