X1288S16-4.5A
| Model | X1288S16-4.5A |
| Description | 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 31 pages (File size: 559K) |
| Chip Manufacturer | XICOR |
Preliminary Information
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of
SDA when the SCL line is high and followed by a stop
bit. The start signal restarts the watchdog timer
counter, resetting the period of the counter back to the
maximum. If another start fails to be detected prior to
the watchdog timer expiration, then the RESET pin
becomes active. In the event that the start signal
occurs during a reset time out period, the start will
have no effect. When using a single START to refresh
watchdog timer, a STOP bit should be followed to reset
the device back to stand-by mode.
LOW VOLTAGE RESET OPERATION
When a power failure occurs, and the voltage to the
part drops below a fixed v
TRIP
voltage, a reset pulse is
issued to the host microcontroller. The circuitry moni-
tors the V
CC
line with a voltage comparator which
senses a preset threshold voltage. Power up and
power down waveforms are shown in Figure 5. The
Low Voltage Reset circuit is to be designed so the
RESET signal is valid down to 1.0V.
When the low voltage reset signal is active, the opera-
tion of any in progress nonvolatile write cycle is unaf-
fected, allowing a nonvolatile write to continue as long
as possible (down to the power on reset voltage). The
low voltage reset signal, when active, terminates in
progress communications to the device and prevents
new commands, to reduce the likelihood of data cor-
ruption.
X1288
V
CC
THRESHOLD RESET PROCEDURE [Optional]
The X1288 is shipped with a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
is not exactly right, or if
higher precision is needed in the V
TRIP
value, the
X1288 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvol-
atile write control signal.
Setting the V
TRIP
Voltage
It is necessary to reset the trip point before setting the
new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold voltage to the V
CC
pin and tie the RESET pin
to the programming voltage V
P
. Then write data 00h to
address 01h. The stop bit following a valid write opera-
tion initiates the V
TRIP
programming sequence. Bring
RESET to V
CC
to complete the operation.
Note:
this
operation may take up to 10 milliseconds to complete
and also writes 00h to address 01h of the EEPROM
array.
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native”
voltage level. For example, if the current V
TRIP
is 4.4V
and the new V
TRIP
must be 4.0V, then the V
TRIP
must
be reset. When V
TRIP
is reset, the new V
TRIP
is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
Figure 4. Watchdog Restart/Time Out
t
RSP
t
RSP
<t
WDO
t
RSP
>t
WDO
t
RST
t
RSP
>t
WDO
t
RST
SCL
SDA
RESET
Start
Stop Start
Note:
All inputs are ignored during the active reset period (t
RST
).
REV 1.1.30 3/24/04
www.xicor.com
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