X1288V14-2.7
| Model | X1288V14-2.7 |
| Description | 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 31 pages (File size: 559K) |
| Chip Manufacturer | XICOR |
Preliminary Information
Figure 8. Valid Data Changes on the SDA Bus
SCL
X1288
SDA
Data Stable
Data Change
Data Stable
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 10. Acknowledge Response From Receiver
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
1
8
9
Figure 11. Slave Address, Word Address, and Data Bytes (128 Byte pages)
Device Identifier
Array
CCR
1
1
0
1
1
0
0
1
1
1
1
R/W
Slave Address Byte
Byte 0
Word Address 1
0
A14
A13
A12
A11
A10
A9
A8
Byte 1
A7
A6
A5
A4
A3
A2
A1
A0
Word Address 0
Byte 2
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
Byte 3
REV 1.1.30 3/24/04
www.xicor.com
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Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 X1288V14-2.7A
|
2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM | XICOR | Preview |
