X24640V20-2.5
| Model | X24640V20-2.5 |
| Description | 400KHz 2-Wire Serial E 2 PROM with Block Lock |
| PDF file | Total 17 pages (File size: 88K) |
| Chip Manufacturer | XICOR |
64K
X24640
400KHz 2-Wire Serial E
2
PROM with Block Lock
TM
DESCRIPTION
8K x 8 Bit
FEATURES
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Save Critical Data with Programmable
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E
2
PROM Array)
—Software Program Protection
—Programmable Hardware Write Protect
In Circuit Programmable ROM Mode
400KHz 2-Wire Serial Interfac
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1
µ
A
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Versions
32 Word Page Write Mode
—Minimizes Total Write Time Per Word
Internally Organized 8K x 8
Bidirectional Data Transfer Protocol
Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8-Lead SOIC
20-Lead TSSOP
8-Lead PDIP
The X24640 is a CMOS Serial E
2
PROM, internally
organized 8K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus. The bus operates at 400 KHz all
the way down to 1.8V.
Three device select inputs (S
0
–S
2
) allow up to eight
devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, FFFFh, provides three write protection features:
Software Write Protect, Block Lock Protect, and
Programmable Hardware Write Protect. The Software
Write Protect feature prevents any nonvolatile writes to
the device until the WEL bit in the Write Protect
Register is set. The Block Lock Protection feature
gives the user four array block protect options, set by
programming two bits in the Write Protect Register.
The Programmable Hardware Write Protect feature
allows the user to install the device with WP tied to
V
CC
, program and Block Lock the desired portions of
the memory array in circuit, and then enable the In
Circuit Programmable ROM Mode by programming the
WPEN bit in the Write Protect Register. After this, the
Block Locked portions of the array, including the Write
Protect Register itself, are permanently protected from
being erased.
FUNCTIONAL DIAGRAM
SERIAL E
2
PROM DATA
AND ADDRESS (SDA)
DATA REGISTER
Y DECODE LOGIC
COMMAND
DECODE
AND
CONTROL
LOGIC
BLOCK LOCK AND
WRITE PROTECT
CONTROL LOGIC
S2
S1
S0
DEVICE
SELECT
LOGIC
WRITE
PROTECT
REGISTER
4K x 8
SERIAL E
2
PROM
ARRAY
8K x 8
2K x 8
SCL
PAGE
DECODE
LOGIC
2K x 8
WP
WRITE VOLTAGE
CONTROL
7038 FM 01
©
Xicor, 1995, 1996 Patents Pending
7038-1.2 4/25/97 T0/C2/D0 SH
1
Characteristics subject to change without notice
