X25128PM-2.7
| Model | X25128PM-2.7 |
| Description | SPI Serial E 2 PROM with Block Lock TM Protection |
| PDF file | Total 15 pages (File size: 80K) |
| Chip Manufacturer | XICOR |
A
PPLICATION
N
OTE
A VA I L A B L E
AN61
128K
X25128
SPI Serial E
2
PROM with Block Lock
TM
Protection
DESCRIPTION
16K x 8 Bit
FEATURES
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2MHz Clock Rate
SPI Modes (0,0 & 1,1)
16K X 8 Bits
—32 Byte Page Mode
Low Power CMOS
—<1
µ
A Standby Current
—<5mA Active Current
2.7V To 5.5V Power Supply
Block Lock Protection
—Protect 1/4, 1/2 or all of E
2
PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
14-Lead SOIC Package
16-Lead SOIC Package
8-Lead PDIP Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
The X25128 is a CMOS 131,072-bit serial E
2
PROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate
data in (SI) and data out (SO) lines. Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same
bus.
The X25128 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25128 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25128 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25128 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
128
16K BYTE
ARRAY
16 X 256
SO
SI
SCK
CS
HOLD
256
32 X 256
COMMAND
DECODE
AND
CONTROL
LOGIC
128
16 X 256
WP
WRITE
CONTROL
AND
TIMING
LOGIC
32
8
Y DECODE
DATA REGISTER
3091 FM F01
©
Xicor Inc. 1994, 1995, 1996 Patents Pending
3091-2.9 5/14/97 T2/C0/D2 SH
1
Characteristics subject to change without notice
