X25163S14I-2.7
| Model | X25163S14I-2.7 |
| Description | Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM |
| PDF file | Total 16 pages (File size: 79K) |
| Chip Manufacturer | XICOR |
64K
32K
16K
FEATURES
X25643/45
X25323/25
X25163/65
DESCRIPTION
8K x 8 Bit
4K x 8 Bit
2K x 8 Bit
Programmable Watchdog Timer & V
CC
Supervisory Circuit w/Serial E
2
PROM
• Programmable Watchdog Timer
• Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
• Save Critical Data With Block Lock
TM
Protection
—Block Lock
TM
Protect 0, 1/4, 1/2 or all of
Serial E
2
PROM Memory Array
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<50
µ
A Max Standby Current, Watchdog On
—<1
µ
A Max Standby Current, Watchdog Off
—<5mA Max Active Current during Write
—<400
µ
A Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564x)
—14-Lead TSSOP (X2532x, X2516x)
—8-Lead SOIC (X2532x, X2516x)
BLOCK DIAGRAM
SI
SO
SCK
CS
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
X - DECODE
LOGIC
These devices combine three popular functions, Watch-
dog Timer, Supply Voltage Supervision, and Serial
E
2
PROM Memory in one package. This combination low-
ers system cost, reduces board space requirements, and
increases reliability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET/RESET signal
after a selectable time-out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET/RESET is asserted until Vcc returns to
proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial
E
2
PROM array with Xicor’s Block Lock
TM
Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
TM
cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
PAGE DECODE LOGIC
32
SERIAL
E
2
PROM
ARRAY
8
RESET/RESET
STATUS
REGISTER
V
CC
LOW
VOLTAGE
SENSE
WATCHDOG
TIMER
WP
PROGRAMMING,
BLOCK LOCK &
ICP ROM CONTROL
HIGH
VOLTAGE
CONTROL
Characteristics subject to change without notice
7036 FRM 01
©
Xicor, Inc. 1994, 1995, 1996 Patents Pending
7049 -1.0 6/20/97 T0/C0/D0 SH
1
