X25169S14I-1.8
| Model | X25169S14I-1.8 |
| Description | V CC Supervisory Circuit w/Serial E 2 PROM |
| PDF file | Total 16 pages (File size: 76K) |
| Chip Manufacturer | XICOR |
64K
32K
16K
FEATURES
X25648/49,
X25328/29,
X25168/69
V
CC
Supervisory Circuit w/Serial E
2
PROM
DESCRIPTION
8K x 8 Bit
4K x 8 Bit
2K x 8 Bit
• Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
• Save Critical Data With Block Lock
TM
Protection
—Block Lock
TM
Protect 0, 1/4, 1/2 or all of
Serial E
2
PROM Memory Array
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<1
µ
A Max Standby Current
—<5mA Max Active Current during Write
—<400
µ
A Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564X)
—14-Lead TSSOP (X2532X, X2516X)
—8-Lead SOIC (X2532X, X2516X)
BLOCK DIAGRAM
SI
SO
SCK
CS
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
These devices combines two popular functions, Supply
Voltage Supervision and Serial E
2
PROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
The user’s system is protected from low voltage condi-
tions by the devices low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET/RESET is asserted until Vcc returns to
proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial
E
2
PROM array with Xicor’s Block Lock
TM
Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
TM
cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
PAGE DECODE LOGIC
X - DECODE
LOGIC
32
SERIAL
E
2
PROM
ARRAY
8
RESET/RESET
STATUS
REGISTER
V
CC
LOW
VOLTAGE
SENSE
WP
PROGRAMMING,
BLOCK LOCK &
ICP ROM CONTROL
HIGH
VOLTAGE
CONTROL
7036 FRM 01
©
Xicor, Inc. 1994, 1995, 1996 Patents Pending
7032 -1.1 6/17/97 T1/C0/D0 SH
1
Characteristics subject to change without notice
