X25642SI-2.7
| Model | X25642SI-2.7 |
| Description | Advanced SPI Serial E 2 PROM with Block Lock TM Protection |
| PDF file | Total 16 pages (File size: 79K) |
| Chip Manufacturer | XICOR |
A
PPLICATION
N
OTE
A V A I LA B L E
AN19 • AN38 • AN41 • AN61
64K
X25642
8K x 8 Bit
Advanced SPI Serial E
2
PROM with Block Lock
TM
Protection
FEATURES
DESCRIPTION
The X25642 is a CMOS 65,536-bit serial E
2
PROM,
internally organized as 8K x 8. The X25642 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25642 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25642 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25642 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25642 utilizes Xicor’s proprietary Direct Write
TM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
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2MHz Clock Rate
Low Power CMOS
—<1
µ
A Standby Current
—<5mA Active Current
2.7V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
8K X 8 Bits
—32 Byte Page Mode
Block Lock Protection
—Protect 1/4, 1/2 or all of E
2
PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
Packages
—8-Lead PDIP
—8-Lead SOIC
—14-Lead SOIC
—20-Lead TSSOP
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
64
8K BYTE
ARRAY
64 X 256
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
64
64 X 256
128
128 X 256
WP
WRITE
CONTROL
AND
TIMING
LOGIC
32
8
Y DECODE
DATA REGISTER
3132 ILL F01.1
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©
Xicor, Inc. 1994, 1995, 1996 Patents Pending
3132-1.0 1/17/97 T5/C0/D1 SH
1
Characteristics subject to change without notice
