Z0538001VSC
| Model | Z0538001VSC |
| Description | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| PDF file | Total 37 pages (File size: 242K) |
| Chip Manufacturer | ZILOG |
Z
ILOG
Z5380 SCSI
AC CHARACTERISTICS
DMA Write (Non-Block Mode) Target Send Cycle Table
No
1
2
3
4
5
6
7
8
9
10
11
12
13
Description
DRQ Low from /DACK Low
/DACK High to DRQ High
Write Enable Width
[1]
/DACK Hold from /IOW High
Data Setup to End of Write Enable
[1]
Data Hold Time from End of /IOW
Width of /EOP Pulse
[2]
/ACK Low to /REQ High
/REQ from End of /DACK (/ACK High)
/ACK Low to DRQ High (Target)
/ACK High to /REQ Low (/DACK High)
Data Hold from Write Enable
Data Setup to /REQ Low (Target)
Min
130
30
100
0
50
40
100
25
30
15
20
15
60
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
125
150
110
150
Notes:
[1] Write Enable is the occurrence of /IOW and /DACK.
[2] /EOP, /IOW, and /DACK must be concurrently Low for at least T7 for proper recognition of the /EOP pulse.
PS97SCC0100
PS009101-0201
23
