ZVN3306A
| Model | ZVN3306A |
| Description | N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET |
| PDF file | Total 3 pages (File size: 50K) |
| Chip Manufacturer | ZETEX |
N-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 60 Volt V
DS
* R
DSon)
=5Ω
ZVN3306A
D
G
S
E-Line
TO92 Compatible
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T
amb
=25°C
Pulsed Drain Current
Gate-Source Voltage
Power Dissipation at T
amb
=25°C
Operating and Storage Temperature Range
SYMBOL
V
DS
I
D
I
DM
V
GS
P
tot
T
j
:T
stg
VALUE
60
270
3
±
20
625
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at T
amb
= 25°C unless otherwise stated).
PARAMETER
Drain-Source Breakdown
Voltage
Gate-Source Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage Drain
Current
On-State Drain Current(1)
Static Drain-Source On-State
Resistance (1)
SYMBOL MIN.
BV
DSS
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(on)
150
35
25
8
5
7
6
8
750
5
60
0.8
2.4
20
0.5
50
MAX. UNIT CONDITIONS.
V
V
nA
µA
µA
mA
Ω
mS
pF
pF
pF
ns
ns
ns
ns
V
DD
≈18V,
I
D
=500mA
V
DS
=18V, V
GS
=0V, f=1MHz
I
D
=1mA, V
GS
=0V
ID=1mA, V
DS
= V
GS
V
GS
=± 20V, V
DS
=0V
V
DS
=60V, V
GS
=0
V
DS
=48V, V
GS
=0V, T=125°C
(2)
V
DS
=18V, V
GS
=10V
V
GS
=10V,I
D
=500mA
V
DS
=18V,I
D
=500mA
Forward Transconductance(1)(2 g
fs
)
Input Capacitance (2)
Common Source Output
Capacitance (2)
Reverse Transfer Capacitance
(2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
(1) Measured under pulsed conditions. Width=300µs. Duty cycle
≤2%
3-375
(
2) Sample test.
