ZVP2110A
| Model | ZVP2110A |
| Description | P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET |
| PDF file | Total 3 pages (File size: 69K) |
| Chip Manufacturer | ZETEX |
P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 100 Volt V
DS
* R
DS(on)
=8Ω
ZVP2110A
D
G
S
E-Line
TO92 Compatible
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T
amb
=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at T
amb
=25°C
Operating and Storage Temperature Range
SYMBOL
V
DS
I
D
I
DM
V
GS
P
tot
T
j
:T
stg
VALUE
-100
-230
-3
±
20
700
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at T
amb
= 25°C unless otherwise stated).
PARAMETER
Drain-Source Breakdown
Voltage
Gate-Source Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage Drain
Current
On-State Drain Current(1)
SYMBOL MIN.
BV
DSS
V
GS(th)
I
GSS
I
DSS
I
D(on)
-750
8
125
100
35
10
7
15
12
15
-100
-1.5
-3.5
20
-1
-100
MAX. UNIT CONDITIONS.
V
V
nA
µA
µA
mA
Ω
mS
pF
pF
pF
ns
ns
ns
ns
V
DD
≈-25V,
I
D
=-375mA
V
DS
=-25V, V
GS
=0V, f=1MHz
I
D
=-1mA, V
GS
=0V
ID=-1mA, V
DS
= V
GS
V
GS
=± 20V, V
DS
=0V
V
DS
=-100 V, V
GS
=0
V
DS
=-80 V, V
GS
=0V, T=125°C
(2)
V
DS
=-25 V, V
GS
=-10V
V
GS
=-10V,I
D
=-375mA
V
DS
=-25V,I
D
=-375mA
Static Drain-Source On-State R
DS(on)
Resistance (1)
Forward Transconductance
(1)(2)
Input Capacitance (2)
Common Source Output
Capacitance (2)
Reverse Transfer
Capacitance (2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
(1) Measured under pulsed conditions. Width=300µs. Duty cycle
≤2%
(2) Sample test.
3-421
Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator
(
3
)
