100% Original And New Integrated Circuits 82P2282PFG Chip In Stock

• Each link can be configured as T1, E1 or J1
• Supports T1/E1/J1 long haul/short haul line interface
• HPS for 1+1 protection without external relays
• Receive sensitivity exceeds -36 dB @ 772 Hz and -43 dB @ 1024
Hz
• Selectable internal line termination impedance: 100 Ω (for T1), 75
Ω / 120 Ω (for E1) and 110 Ω (for J1)
• Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) line encoding/decoding
• Provides T1/E1/J1 short haul pulse templates, long haul LBO (per
ANSI T1.403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22 dB) and userprogrammable arbitrary pulse template
• Supports G.772 non-intrusive monitoring
• Supports T1.102 line monitor
• Transmit line short-circuit detection and protection
• Separate Transmit and Receive Jitter Attenuators (2 per link)
• Indicates the interval between the write pointer and the read pointer
of the FIFO in JA
• Loss of signal indication with programmable thresholds according
to ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1)
• Supports Analog Loopback, Digital Loopback and Remote Loopback
• Each receiver and transmitter can be individually powered down

Name Type Pin No. Description
Line and System Interface
RTIP[1]
RTIP[2]
RRING[1]
RRING[2]
Input 27
12
28
11
RTIP[1:2] / RRING[1:2]: Receive Bipolar Tip/Ring for Link 1 ~ 2
These pins are the differential line receiver inputs.
TTIP[1]
TTIP[2]
TRING[1]
TRING[2]
Output 21
18
22
17
TTIP[1:2] / TRING[1:2]: Transmit Bipolar Tip/Ring for Link 1 ~ 2
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic
high on the THZ pin sets all these pins to high impedance state. When the T_HZ bit (b4, T1/J1-023H,... / b4, E1-
023H,...) * is set to ‘1’, the TTIPn/TRINGn pins in the corresponding link are set to high impedance state.
Besides, TTIPn/TRINGn will also be set to high impedance state by other ways (refer to Chapter 3.25 Line Driver for
details).
RSD[1] / MRSD
RSD[2]
Output 79
71
RSD[1:2]: Receive Side System Data for Link 1 ~ 2
The processed data stream is output on these pins.
In Receive Clock Master mode, the RSDn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSDn pins are
updated on the active edge of the corresponding RSCKn or both two RSDn pins are updated on the active edge of
RSCK[1].
MRSD: Multiplexed Receive Side System Data for Link 1 ~ 2
In Receive Multiplexed mode, the MRSD pin is used to output the processed data stream. Using a byte-interleaved
multiplexing scheme, the MRSD pin outputs the data from Link 1 and Link 2. The data on the MRSD pin is updated on
the active edge of the MRSCK.
RSIG[1] / MRSIG
RSIG[2]
Output 78
70
RSIG[1:2]: Receive Side System Signaling for Link 1 ~ 2
The extracted signaling bits are output on these pins. They are located in the lower nibble (b5 ~ b8) and are channel/
timeslot-aligned with the data output on the corresponding RSDn pin.
In Receive Clock Master mode, the RSIGn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSIGn pins are
updated on the active edge of the corresponding RSCKn or both two RSIGn are updated on the active edge of
RSCK[1].
MRSIG: Multiplexed Receive Side System Signaling for Link 1 ~ 2
In Receive Multiplexed mode, the MRSIG pin is used to output the extracted signaling bits. The signaling bits are
located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data output on the MRSD pin. Using the
byte-interleaved multiplexing scheme, the MRSIG pin outputs the signaling bits from Link 1 and Link 2. The signaling
bits on the MRSIG pin is updated on the active edge of the MRSCK.