ISO1540DRDGTL ISOL 2500VRMS 2CH I2C

1 Features
• Isolated bidirectional, I2C compatible,
communication
• Supports up to 1-MHz operation
• 3-V to 5.5-V supply range
• Open-drain outputs With 3.5-mA Side 1 and 35-
mA Side 2 sink current capability
• –40°C to +125°C operating temperature
• ±50-kV/µs transient immunity (Typical)
• HBM ESD protection of 4 kV on all pins;
8 kV on bus pins
• Safety-related certifications:
– 4242-VPK isolation per DIN EN IEC 60747-17
(VDE 0884-17)
– 2500-VRMS isolation for 1 minute per UL 1577
– CSA approval per IEC 62368-1 end equipment
standard
– CQC basic insulation per GB4943.1-2011
2 Applications
• Isolated I2C buses
• SMBus and PMBus interfaces
• Open-drain networks
• Motor control systems
• Battery management
• I
2C level shifting
3 Description
The ISO1540 and ISO1541 devices are low-power,
bidirectional isolators that are compatible with I2C interfaces. These devices have logic input and output
buffers that are separated by Texas Instruments Capacitive Isolation technology using a silicon dioxide
(SiO2) barrier. When used with isolated power supplies, these devices block high voltages, isolate
grounds, and prevent noise currents from entering
the local ground and interfering with or damaging sensitive circuitry.
This isolation technology provides for function,
performance, size, and power consumption advantages when compared to optocouplers. The
ISO1540 and ISO1541 devices enable a complete isolated I2C interface to be implemented within a small form factor.
The ISO1540 has two isolated bidirectional channels
for clock and data lines while the ISO1541 has a bidirectional data and a unidirectional clock channel.
The ISO1541 is useful in applications that have a
single controller while the ISO1540 is suitable for multi-controller applications. For applications where
clock stretching by the target is possible, the ISO1540 device should be used.
Isolated bidirectional communication is accomplished within these devices by offsetting the low-level output
voltage on side 1 to a value greater than the highlevel input voltage on side 1, thus preventing an
internal logic latch that otherwise would occur with standard digital isolators.