C0402T609J5GCC
| Model | C0402T609J5GCC |
| Description | Ceramic Capacitor, Multilayer, Ceramic, 50V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.000006uF, Surface Mount, 0402, CHIP, ROHS COMPLIANT |
| PDF file | Total 18 pages (File size: 1M) |
| Chip Manufacturer | KEMET |
SMD MLCCs – Commercial Off-the-Shelf (COTS) for Higher Reliability Applications, C0G Dielectric, 10VDC-200VDC
Figure 2 – Punched (Paper) Carrier Tape Dimensions
T
ØDo
P
2
Po
[10 pitches cumulative
tolerance on tape ±0.2 mm]
E
1
A
0
F
E
2
W
Bottom Cover Tape
B
0
T
1
P
1
Top Cover Tape
T
1
Center Lines of Cavity
Cavity Size,
See
Note 1, Table 7
Bottom Cover Tape
G
User Direction of Unreeling
Table 7 – Punched (Paper) Carrier Tape Dimensions
Metric will govern
Constant Dimensions — Millimeters (Inches)
Tape Size
8mm
D
0
1.5 +0.10-0.0
(0.059 +0.004, -0.0)
E
1
1.75 ±0.10
(0.069 ±0.004)
P
0
4.0 ±0.10
(0.157 ±0.004)
P
2
2.0 ±0.05
(0.079 ±0.002)
T
1
Max
0.10
(.004) Max.
G Min
0.75
(.030)
R Ref.
Note 2
25
(.984)
Variable Dimensions — Millimeters (Inches)
Tape Size
8mm
8mm
Pitch
Half (2mm)
Single (4mm)
E2 Min
6.25
(0.246)
F
3.5 ± 0.05
(0.138 ± 0.002)
2.0 ± 0.05
(0.079 ± 0.002)
4.0 ± 0.10
(0.157 ± 0.004)
P
1
T Max
1.1
(0.098)
W Max
8.3
(0.327)
8.3
(0.327)
A
0
B
0
Note 5
1. The cavity defined by A
0
, B
0
and T shall surround the component with sufficient clearance that:
a) the component does not protrude beyond either surface of the carrier tape.
b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.
d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).
e) see Addendum in EIA Document 481 for standards relating to more precise taping requirements.
2. The tape with or without components shall pass around R without damage (see Figure 5).
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com
C1026_COTS_C0G • 6/6/2011
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