I17120XYIR01
| Model | I17120XYIR01 |
| Description | Speech Synthesizer With RCDG, 240s, DIE |
| PDF file | Total 24 pages (File size: 351K) |
| Chip Manufacturer | WINBOND |
ISD1700 SERIES
7.2 SPI O
PERATION
T
SSH
T
SSmin
SS
T
SSS
T
SCKlow
T
SCKhi
SCLK
T
DIS
T
DIH
MOSI
T
PD
(TRISTATE)
LSB
MSB
T
DF
MISO
LSB
MSB
Figure 12.8: SPI Operation
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
SS
Setup Time
T
SSS
T
SSH
T
DIS
T
DIH
T
PD
T
DF
T
SSmin
T
SCKhi
T
SCKlow
F
0
500
500
200
200
500
500
1
400
400
1,000
50
nsec
nsec
nsec
nsec
nsec
nsec
µsec
nsec
nsec
KHz
msec
SS
Hold Time
Data in Setup Time
Data in Hold Time
Output Delay
Output Delay to HighZ
SS
HIGH
SCLK High Time
SCLK Low Time
CLK Frequency
Power-Up Delay
Notes:
[1]
[1]
T
PUD
The value shown is based upon 8 kHz sampling frequency. Delay increases proportionally for
slower sampling frequency.
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