I1P-L67202V-55
| Model | I1P-L67202V-55 |
| Description | FIFO, 1KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28 |
| PDF file | Total 16 pages (File size: 147K) |
| Chip Manufacturer | TEMIC |
L 67201/L 67202
AC Test Conditions
Input pulse levels
Input rise/Fall times
: 5 ns
Input timing reference levels
Output reference levels
Output load
: Gnd to 3.0 V
: 1.5 V
: 1.5 V
: See figure 7
TO
OUTPUT
PIN
780
Ω
MATRA MHS
Figure 7. Output Load.
3.3 V
600
Ω
30 pF*
* includes jig and scope capacitance
SYMBOL
(16)
SYMBOL
(17)
PARAMETER (18) (22)
L 67201/202
– 55
MIN.
MAX.
–
55
–
–
–
–
–
30
–
–
–
–
–
–
–
–
–
–
–
–
–
65
65
50
50
–
50
50
65
65
L 67201/202
– 60
MIN.
75
–
15
60
–
–
5
–
75
60
15
30
5
75
60
60
15
75
60
60
15
–
–
–
–
60
–
–
–
–
L 67201/202
– 65
MIN.
80
–
15
65
10
15
5
–
80
65
15
30
10
80
65
65
15
80
65
65
15
–
–
–
–
65
–
–
–
–
UNIT
MAX.
–
60
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
75
75
55
55
–
55
55
75
75
MAX.
–
65
–
–
–
–
–
30
–
–
–
–
–
–
–
–
–
–
–
–
–
75
75
60
60
–
60
60
75
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ CYCLE
TRLRL
TRLQV
TRHRL
TRLRH
TRLQX
TWHQX
TRHQX
TRHQZ
TWLWL
TWLWH
TWHWL
TDVWH
TWHDX
TRSLWL
TRSLRSH
TWHRSH
TRSHWL
TRTLWL
TRTLRTH
TWHRTH
TRTHWL
FLAGS
TRSLEFL
TRSLFFH
TRLEFL
TRHFFH
TEFHRH
TWHEFH
TWLFFL
TWLHFL
TRHHFH
tEFL
tHFH, tFFH
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
Reset to EF low
Reset to HF/FF high
Read low to EF low
Read high to FF high
Read width after EF high
Write high to EF high
Write low to FF low
Write low to HF low
Read high to HF high
–
–
–
–
55
–
–
–
–
tRC
tA
tRR
tRPW
tRLZ
tWLZ
tDV
tRHZ
tWC
tWPW
tWR
tDS
tDH
tRSC
tRS
tRSS
tRSR
tRTC
tRT
tRTS
tRTR
Read cycle time
Access time
Read recovery time
Read pulse width (19)
Read low to data low Z (20)
Write low to data low Z (20, 21)
Data valid from read high
Read high to data high Z (20)
Write cycle time
Write pulse width (19)
Write recovery time
Data set-up time
Data hold time
Reset cycle time
Reset pulse width (19)
Reset set-up time
Reset recovery time
Retransmit cycle time
Retransmit pulse width (19)
Retransmit set-up time (20)
Retransmit recovery time
70
–
15
55
10
15
5
–
70
55
15
30
5
70
55
55
15
70
55
55
15
WRITE CYCLE
RESET CYCLE
RETRANSMIT CYCLE
10
Rev. C (10/11/95)
