I3K-L67140L-55
| Model | I3K-L67140L-55 |
| Description | Dual-Port SRAM, 1KX8, 55ns, CMOS, PDIP48, 0.600 INCH, PLASTIC, DIP-48 |
| PDF file | Total 16 pages (File size: 196K) |
| Chip Manufacturer | TEMIC |
L67130/L67140
1 K
×
8 CMOS Dual Port RAM 3.3 Volt
Introduction
The L67130/67140 are very low power CMOS dual port
static RAMs organized as 1024
×
8. They are designed to
be used as a stand-alone 8 bits dual port RAM or as a
combination MASTER/SLAVE dual port for 16 bits or
more width systems. The MHS MASTER/SLAVE dual
port approach in memory system applications results in
full speed, error free operation without the need for
additional discrete logic.
Master and slave devices provide two independent ports
with separate control, address and I/O pins that permit
independent, asynchronous access for reads and writes to
any location in the memory. An automatic power down
feature controlled by CS permits the onchip circuitry of
each port in order to enter a very low stand by power
mode.
Using an array of eight transistors (8T) memory cell and
fabricated with the state of the art 1.0
µm
lithography
named SCMOS, the M67130/140 combine an extremely
low standby supply current (typ = 1.0
µA)
with a fast
access time at 45 ns over the full temperature range. All
versions offer battery backup data retention capability
with a typical power consumption at less than 5
µW.
For military/space applications that demand superior
levels of performance and reliability the L67130/67140
is processed according to the methods of the latest
revision of the MIL STD 883 (class B or S) and/or ESA
SCC 9000.
Features
D
Single 3.3 V
±
0.3 volt power supply
D
Fast access time
45 ns(*) to 70 ns
D
67130L/67140L low power
67130V/67140V very low power
D
Expandable data bus to 16 bits or more using master/slave
devices when using more than one device.
(*) Preliminary
D
D
D
D
D
D
On chip arbitration logic
BUSY output flag on master
BUSY input flag on slave
INT flag for port to port communication
Fully asynchronous operation from either port
Battery backup operation : 2 V data retention
MATRA MHS
Rev. D (19 Fev. 97)
1
