M1021-12I125.0000LF
| Model | M1021-12I125.0000LF |
| Description | Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| PDF file | Total 10 pages (File size: 440K) |
| Chip Manufacturer | IDT |
Product Data Sheet
M1020/21
VCSO B
ASED
C
LOCK
PLL
G
ENERAL
D
ESCRIPTION
The M1020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
F
EATURES
◆
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (LOL) output pin
◆
Narrow Bandwidth control input (NBW pin)
◆
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) / SDH
(G.813) MTIE and TDEV compliance during reselection
◆
Pin-selectable feedback and reference divider ratios
◆
Industrial temperature grade available
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M1020-11-155.5200 or M1021-11-155.5200
Input Reference
Clock (MHz)
(M1020)
(M1021)
PLL Ratio
(Pin Selectable)
(M1020)
(M1021)
Output Clock
(MHz)
(Pin Selectable)
19.44 or 38.88
77.76
155.52
622.08
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
NBW
LOL
MR_SEL3:0
P_SEL1:0
Figure 2: Simplified Block Diagram
M1020/21 Datasheet Rev 1.0
M1020/21 VCSO Based Clock PLL
Revised 28Jul2004
●
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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tel (508) 852-5400
