M1033-16-155.5200T
| Model | M1033-16-155.5200T |
| Description | CLCC-36, Reel |
| PDF file | Total 14 pages (File size: 201K) |
| Chip Manufacturer | IDT |
Integrated
Circuit
Systems, Inc.
General Guidelines for M and R Divider Selection
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Preliminary Information
General guidelines for M/R divider selection (see
following pages for more detail):
F
UNCTIONAL
D
ESCRIPTION
The M1033/34 is a PLL (Phase Locked Loop) based
clock generator that generates an output clock synchro-
nized to one of two selectable input reference clocks.
An internal high ‘Q’ SAW delay line provides low jitter
signal performance.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in
Tables 3 and 4 on pg. 3.
These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
The M1033/34 includes a Loss of Reference (
LOR
)
indicator for the currently selected reference input which
can be used to provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
An automatic input reselection feature, or “AutoSwitch”
is also included in the M1033/34. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails (when LOR goes high).
Reference selection is non-revertive, meaning that only
one reference reselection will be made each time that
AutoSwitch is re-enabled.
In addition to the AutoSwitch feature, a Phase Build-out
option can be ordered with the device.
•
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
.
P Divider Look-Up Table (LUT)
The
P_SEL1
and
P_SEL0
pins select the post-PLL divider
value P. The output frequency of the SAW can be
divided by
1
or
2
or the output can be TriStated as
specified in Table 5.
P_SEL1:0
P Value
2
1
2
TriState
M1033-155.5200 or M1034-155.5200
0
0
1
1
0
1
0
1
Output Frequency (MHz)
77.76
155.52
77.76
N/A
Table 5: P Divider Look-Up Table (LUT)
M1033/34 Preliminary Information 0.1
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
4 of 14
Networking & Communications
●
Revised 07Apr2005
w w w. i c s t . c o m
●
tel (508) 852-5400
