M1034-16I167.3316
| Model | M1034-16I167.3316 |
| Description | PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| PDF file | Total 14 pages (File size: 201K) |
| Chip Manufacturer | IDT |
Integrated
Circuit
Systems, Inc.
Preliminary Information
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
MR_SEL3
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
MR_SEL2
MR_SEL0
MR_SEL1
LOR
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M1033/34 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1033/34 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
◆
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Reference (LOR) output pin; Narrow Bandwidth
control input (NBW pin)
◆
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
◆
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
◆
Phase Build-out only upon MUX reselection option
(PBOM)
◆
Pin-selectable feedback and reference divider ratios
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
28
29
30
31
32
33
34
35
36
M1033
M1034
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
F
EATURES
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M1033-11-155.5200 or M1034-11-155.5200
Input Reference
Clock (MHz)
(M1033)
(M1034)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
PLL Ratio
(Pin Selectable)
(M1033)
(M1034)
Output Clock
(MHz)
(Pin Selectable)
19.44 or 38.88
77.76
155.52
622.08
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
M1033/34
NBW
MUX
Loop Filter
DIF_REF0
nDIF_REF0
Activity
Detector
0
PLL
Phase
Detector
R Div
DIF_REF1
nDIF_REF1
Activity
Detector
1
0
1
VCSO
LOR
REF_ACK
Auto
Ref Sel
M Divider
P Divider
(1, 2, or TriState)
TriState
FOUT
nFOUT
REF_SEL
AUTO
MR_SEL3:0
P_SEL1:0
4
2
1
0
M / R Divider
LUT
P Divider
LUT
Figure 2: Simplified Block Diagram
M1033/34 Preliminary Information 0.1
M1033/34 VCSO Based Clock PLL with AutoSwitch
Revised 07Apr2005
●
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
Networking & Communications
●
w w w. i c s t . c o m
●
tel (508) 852-5400
