M11B1644SA-60T
| Model | M11B1644SA-60T |
| Description | EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, TSOP2-26/24 |
| PDF file | Total 16 pages (File size: 200K) |
| Chip Manufacturer | ESMT |
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Notes :
1.
2.
Enables on-chip refresh and address counters.
V
IH
(min) and V
IL
(max) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
.
In addition to meet the transition rate specification, all
input signals must transit between V
IH
and V
IL
in a
monotonic manner.
Assume that t
RCD
< t
RCD
(max). If t
RCD
is greater than
the maximum recommended value shown in this
table, t
RAC
will increase by the amount that t
RCD
exceeds the value shown.
Assume that t
RCD
≥
t
RCD
(max)
If
CAS
is low at the falling edge of
RAS
, data-out
will be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer,
CAS
and
RAS
must be pulsed high.
Operation within the t
RCD
limit ensures that t
RCD
(max)
can be met, t
RCD
(max) is specified as a reference
point only ; if t
RCD
is greater than the specified t
RCD
(max) limit, access time is controlled by t
CAC
.
Operation within the t
RAD
limit ensures that t
RAD
(max)
can be met. t
RAD
(max) is specified as a reference
point only ; if t
RAD
is greater than the specified t
RAD
(max) limit, access time is controlled by t
AA
.
Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
t
OFF1
(max) defines the time at which the output
achieves the open circuit condition ; it is not a
reference to V
OH
or V
OL
.
t
WCS
, t
RWD
, t
AWD
and t
CWD
are restrictive operating
parameters in LATE WRITE and READ-MODIFY-
WRITE cycle only. If t
WCS
≥
t
WCS(min)
, the cycle is an
EARLY WRITE cycle and the data output will remain
an open circuit throughout the entire cycle. If t
RWD
≥
t
RWD(min)
, t
AWD
≥
tAWD(min)
and t
CWD
≥
t
CWD(min)
, the
M11B1644A / M11B1644SA
M11L1644A / M11L1644SA
3.
cycle is READ-WRITE and the data output will contain
data read from the selected cell. If neither of the above
conditions is met, the state of I/O (at access time and
until
CAS
and
RAS
or
OE
go back to V
IH
) is
indeterminate.
OE
held high and
WE
taken low
after
CAS
goes low result in a LATE WRITE (
OE
-
controlled) cycle.
12. Those parameters are referenced to
CAS
leading
edge in EARLY WRITE cycles and
WE
leading edge
in LATE WRITE or READ-MODIFY- WRITE cycles.
13. During a READ cycle, if
OE
is low then taken HIGH
before
CAS
goes high, I/O goes open, if
OE
is tied
permanently low, a LATE WRITE or READ-MODIFY-
WRITE operation is not possible.
14. An initial pause of 200
µ
s is required after power-up
followed by eight
RAS
refresh cycles (
RAS
only or
CBR) before proper device operation is assured. The
eight
RAS
cycle wake-ups should be repeated any
time the t
REF
refresh requirement is exceeded.
15. WRITE command is defined as
WE
going low.
16. LATE WRITE and READ-MODIFY-WRITE cycles must
have both tOFF2 and t
OEH
met (
OE
high during
WRITE cycle) in order to ensure that the output buffers
will be open during the WRITE cycles.
17. The I/Os open during READ cycles once tOFF1 or
tOFF2 occur.
18. Each
CAS
must meet minimum pulse width.
19. All IOs controlled by
OE
, regardless
CAS
.
20. Self refresh mode is initiated by performing a CBR
refresh cycle and holding
RAS
low for the specified
tRASS. Self refresh mode is terminated by rising
RAS
high for a minimum time of tRPS.
21. For all of the refresh mode except the distributed CBR
refresh mode, all rows must be refreshed within the
refresh rate before and after self refresh.
4.
5.
6.
7.
8.
9.
10.
11.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.1
6/16
