S0700KC17V
| Model | S0700KC17V |
| Description | Symmetrical GTO SCR, 870A I(T)RMS, 1700V V(DRM), 170V V(RRM), 1 Element |
| PDF file | Total 15 pages (File size: 181K) |
| Chip Manufacturer | IXYS |
WESTCODE
An IXYS Company
2 Characteristics
Symmetrical Gate Turn-Off Thyristor type S0700KC17#
2.1 Instantaneous on-state voltage
Measured using a 500µs square pulse, see also the curves of figure 2 for other values of I
TM
.
2.2 Latching and holding current
These are considered to be approximately equal and only the latching current is measured, type test only
as outlined below. The test circuit and wave diagrams are given in diagram 4. The anode current is
monitored on an oscilloscope while V
D
is increased, until the current is seen to flow during the un-gated
period between the end of I
G
and the application of reverse gate voltage. Test frequency is 100Hz with I
GM
& I
G
as for t
d
of characteristic data.
I
GM
I
G
200µs
Gate current
15V
200µs
R1
Unlatched
Anode current
unlatched condition
CT
C1
DUT
Gate-drive
Vs
Anode current
Latched condition
Latched
Diagram 4, Latching test circuit and waveforms.
2.3 Critical dv/dt
The gate conditions are the same as for 1.1, this characteristic is for off-state only and does not relate to
dv/dt at turn-off. The measurement, type test only, is conducted using the exponential ramp method as
shown in diagram 5. It should be noted that GTO thyristors have a poor static dv/dt capability if the gate is
open circuit or R
GK
is high impedance. Typical values: - dv/dt<30V/µs for R
GK
>10Ω.
Diagram 5, Definition of dV/dt.
2.4 Off-state leakage.
For I
DRM
& I
RRM
see notes 1.1 & 1.2 for gate leakage I
GK
, the off-state gate circuit is required to sink this
leakage and still maintain minimum of –2 Volts. See diagram 6.
Diagram 6.
Data Sheet. Type S0700KC17# Issue 1
Page 5 of 15
July, 2004
