S0700KC17V
| Model | S0700KC17V |
| Description | Symmetrical GTO SCR, 870A I(T)RMS, 1700V V(DRM), 170V V(RRM), 1 Element |
| PDF file | Total 15 pages (File size: 181K) |
| Chip Manufacturer | IXYS |
WESTCODE
An IXYS Company
Symmetrical Gate Turn-Off Thyristor type S0700KC17#
In addition to the turn-on time figures given in the characteristics data, the curves of figure 9 give the
relationship of t
gt
to di/dt and I
GM
. The data in the curves of figures 7 & 8, gives the turn-on losses both with
and without snubber discharge, a snubber of the form given in diagram 2 is assumed. Only typical losses
are given due to the large number of variables which effect E
on
. It is unlikely that all negative aspects
would appear in any one application, so typical figures can be considered as worst case. Where the turn-
on loss is higher than the figure given it will in most cases be compensated by reduced turn-off losses, as
variations in processing inversely effect many parameters. For a worst case device, which would also
have the lowest turn-off losses, E
on
would be 1.5x values given in the curves of figures 7 & 8. Turn-on
losses are measured over the integral period specified below:-
10
µs
Eon
=
∫
iv
.
dt
0
The turn-on loss can be sub-divided into two component parts, firstly that associated with t
gt
and secondly
the contribution of the voltage tail. For this series of devices t
gt
contributes 50% and the voltage tail 50%
(These figures are approximate and are influenced by several second order effects). The loss during t
gt
is
greatly affected by gate current and as with turn-on time (figure 9), it can be reduced by increasing I
GM
.
The turn-on loss associated with the voltage tail is not effected by the gate conditions and can only be
reduced by limiting di/dt, where appropriate a turn-on snubber should be used. In applications where the
snubber is discharged through the GTO thyristor at turn-on, selection of discharge resistor will effect E
on
.
The curves of figure 8 are given for a snubber as shown in diagram 2, with R=5Ω, this is the lowest
recommended value giving the highest E
on
, higher values will reduce E
on
.
2.7 Turn-off characteristics
The basic circuit used for the turn-off test is given in diagram 10. Prior to the negative gate pulse being
applied constant current, equivalent to I
TGQ
, is established in the DUT. The switch S
x
is opened just before
DUT is gated off with a reverse gate pulse as specified in the characteristic/data curves. After the period
t
gt
voltage rises across the DUT, dv/dt being limited by the snubber circuit. Voltage will continue to rise
across DUT until D
c
turns-on at a voltage set by the active clamp C
c
, the voltage will be held at this value
until energy stored in L
x
is depleted, after which it will fall to V
DC
.The value of L
x
is selected to give
required V
D
Over the full tail time period. The overshoot voltage V
DM
is derived from L
c
and forward voltage
characteristic of D
C
, typically V
DM
=1.2V
D
to 1.5V
D
depending on test settings. The gate is held reverse
biased through a low impedance circuit until the tail current is fully extinguished.
L
c
D
c
S
x
R
L
L
x
R
s
C
c
CT
D
s
C
s
Gate-
drive
DUT
C
d
V
d
V
c
i
D
X
RCD snubber
Diagram 10, Turn-off test circuit.
The definitions of turn-off parameters used in the characteristic data are given in diagram 11.
Data Sheet. Type S0700KC17# Issue 1
Page 7 of 15
July, 2004
