W134S
| Model | W134S |
| Description | Direct Rambus Clock Generator |
| PDF file | Total 12 pages (File size: 200K) |
| Chip Manufacturer | CYPRESS |
W134M/W134S
Timing Diagrams
Power-down Exit and Entry
PwrDnB
Clk/ClkB
Output Enable Control
StopB
t
CLKON
t
CLKOFF
t
CLKSETL
t
POWERUP
t
POWERDN
t
ON
t
STOP
Clk/ClkB
Output clock Clock enabled
not specified and glitch-free
glitches may
occur
Clock output settled within
50 ps of the phase before
disabled
Figure 5. State Transition Timing Diagrams
Mult0 and/or Mult1
t
MULT
Clk/ClkB
Figure 6. Multiply Transition Timing
Table 8. State Transition Latency Specifications
Transition Latency
Transition
A
C
K
G
H
M
J
From
Power-down
Power-down
Power-down
V
DD
ON
V
DD
ON
V
DD
ON
Normal
To
Normal
Clk Stop
Test
Normal
Clk Stop
Test
Normal
Parameter
t
POWERUP
t
POWERUP
t
POWERUP
t
POWERUP
t
POWERUP
t
POWERUP
t
MULT
Max.
3 ms
3 ms
3 ms
3 ms
3 ms
3 ms
1 ms
Description
Time from PwrDnB to Clk/ClkB output settled
(excluding t
DISTLOCK
).
Time from PwrDnB until the internal PLL and clock has
turned ON and settled.
Time from PwrDnB to Clk/ClkB output settled
(excluding t
DISTLOCK
).
Time from V
DD
is applied and settled until Clk/ClkB
output settled (excluding t
DISTLOCK
).
Time from V
DD
is applied and settled until internal PLL
and clock has turned ON and settled.
Time from V
DD
is applied and settled until internal PLL
and clock has turned ON and settled.
Time from when Mult0 or Mult1 changed until Clk/ClkB
output resettled (excluding t
DISTLOCK
).
Document #: 38-07426 Rev. *B
Page 6 of 12
