W134S
| Model | W134S |
| Description | Direct Rambus Clock Generator |
| PDF file | Total 12 pages (File size: 200K) |
| Chip Manufacturer | CYPRESS |
W134M/W134S
Device Characteristics
Parameter
t
CYCLE
t
J
Clock Cycle Time
Cycle-to-Cycle Jitter at Clk/ClkB
Total Jitter over 2, 3, or 4 Clock
266-MHz Cycle-to-Cycle
t
STEP
t
ERR,PD
t
ERR,SSC
V
X,STOP
V
X
V
COS
V
OH
V
OL
r
OUT
I
OZ
I
OZ,STOP
DC
t
DC,ERR
t
R,
t
F
t
CR,CF
[9]
Description
Min.
2.5
–
–
–
–
1
–100
–100
1.1
1.3
0.4
–
1.0
Max.
3.75
60
100
100
160
–
100
100
2.0
1.8
0.6
2.0
–
50
50
500
60
50
500
100
Unit
ns
ps
ps
ps
ps
ps
ps
ps
V
V
V
V
V
Ω
µA
µA
%t
CYCLE
ps
ps
ps
Cycles
[9]
Jitter
[10]
266-MHz Total Jitter over 2, 3, or 4 Clock Cycles
[10]
Phase Aligner Phase Step Size (at Clk/ClkB)
Phase Detector Phase Error for Distributed Loop Measured at
PclkM-SynclkN (rising edges) (does not include clock jitter)
PLL Output Phase Error when Tracking SSC
Output Voltage during Clk Stop (StopB=0)
Differential Output Crossing-Point Voltage
Output Voltage Swing (p-p single-ended)
[11]
Output High Voltage
Output Low voltage
Output Dynamic Resistance (at
pins)
[12]
Output Current during Hi-Z (S0 = 0, S1 = 1)
Output Current during Clk Stop (StopB = 0)
Output Duty Cycle over 10,000 Cycles
Output Cycle-to-Cycle Duty Cycle Error
Output Rise and Fall Times (measured at 20%–80% of output voltage)
Difference between Output Rise and Fall Times on the Same Pin of a
Single Device (20%–80%)
12
–
–
40
–
250
–
Notes:
9. Output Jitter spec measured at t
CYCLE
= 2.5 ns.
10. Output Jitter Spec measured at t
CYCLE
= 3.75 ns.
11. V
COS
= V
OH
–V
OL.
12. r
OUT
= DV
O
/ D I
O
. This is defined at the output pins.
Document #: 38-07426 Rev. *B
Page 9 of 12
