W159
| Model | W159 |
| Description | Spread Spectrum System FTG for SMP Systems |
| PDF file | Total 11 pages (File size: 138K) |
| Chip Manufacturer | CYPRESS |
W159
Maximum Allowed Current
Table 2. Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
V
DDQ2
=2.625V
All static inputs=V
DDQ3
or V
SS
300 µA
120 mA
120 mA
Max. 3.3V supply consumption
Max. discrete cap loads,
V
DDQ3
=3.465V
All static inputs=V
DDQ3
or V
SS
500 µA
160 mA
160 mA
Condition
Power-down Mode
(PWRDWN#=0)
Full Active 100 MHz
SEL133/100#=0
Full Active 133 MHz
SEL133/100#=1
Table 3. Clock Enable Configuration
[2, 3, 4]
PWRDWN#
0
1
CPUCLK
LOW
ON
CPUdiv2
LOW
ON
APIC
LOW
ON
3V66
LOW
ON
3V33
LOW
ON
48MHz
LOW
ON
REF
LOW
ON
OSC.
OFF
ON
VCOs
OFF
ON
Table 4. Power Management State Transition
Signal
PWRDWN#
Signal State
1 (normal operation)
0 (power down)
Latency
[5]
3 ms
2 PCI clocks (max.)
Timing Diagram
PWRDWN# Timing Diagram
[6, 7, 8, 9, 10]
CPUCLK
(internal)
PCI
(internal)
PWRDWN#
CPUCLK
(external)
PCI
(external)
VCO
Crystal
Notes:
2. LOW means outputs held static LOW as per latency requirement below.
3. ON means active.
4. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
5. Power-up latency is when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
6. All internal timing is referenced to the CPUCLK.
7. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
8. PWRDWN is an asynchronous input and metastable conditions could exist. This signal is synchronized by the W159 internally.
9. The shaded sections on the VCO and the Crystal signals indicate an active clock.
10. Diagrams shown with respect to 133 MHz. Similar operation when CPUCLK is 100 MHz.
Document #: 38-07163 Rev. *A
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