W159
| Model | W159 |
| Description | Spread Spectrum System FTG for SMP Systems |
| PDF file | Total 11 pages (File size: 138K) |
| Chip Manufacturer | CYPRESS |
W159
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
f
D
m/n
t
R
t
F
t
D
f
ST
Description
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
25
0.5
0.5
45
Min.
Typ.
48.008
+167
57/17
2
2
55
3
V/ns
V/ns
%
ms
Max.
Unit
MHz
ppm
Z
o
Ω
2.5V AC Electrical Characteristics
T
A
= 0°C to +70°C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5%
f
XTL
= 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
[20]
CPU Clock Outputs, CPU0:6 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
Description
Period
High Time
Low Time
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Test Condition/Comments
Measured on rising edge at 1.25V
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Measured from 2.0V to 0.4V
Measured on rising and falling edge at
1.25V
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
Measured on rising edge at 1.25V
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
7.5
1.87
1.67
1
1
45
4
4
55
250
7.65
CPU = 100 MHz
Typ. Max. Unit
10.2
ns
ns
ns
4
4
55
250
V/ns
V/ns
%
ps
10
3.0
2.8
1
1
45
Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
t
SK
f
ST
Output Skew
Frequency Stabiliza-
tion from Power-up
(cold start)
AC Output Impedance
175
3
175
3
ps
ms
Z
o
20
Ω
Note:
20. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
Document #: 38-07163 Rev. *A
Page 8 of 11
