W161H
| Model | W161H |
| Description | Processor Specific Clock Generator, 133MHz, CMOS, PDSO48, 0.300 INCH, MO-118AA, SSOP-48 |
| PDF file | Total 10 pages (File size: 115K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
PCI Clock Outputs, PCI0:9 (Lump Capacitance Test Load = 30 pF
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
t
SK
t
O
f
ST
Description
Period
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Output Skew
3V66 to PCI Clock Skew
Frequency Stabilization
from Power-up (cold
start)
AC Output Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
[9]
W161
Min.
30
12
12
1
1
45
Typ.
Max.
Unit
ns
ns
ns
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V.
Covers all 3V66/PCI outputs. Measured on rising
edge at 1.5V. 3V66 leads PCI output.
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
Average value during switching transition. Used for
determining series termination value.
4
4
55
500
500
V/ns
V/ns
%
ps
ps
ns
ms
1.5
3
3
Z
o
15
Ω
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
f
t
R
t
F
t
D
f
ST
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization from
Power-up (cold start)
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
25
0.5
0.5
45
Min.
Typ.
14.318
2
2
55
3
V/ns
V/ns
%
ms
Max.
Unit
Z
o
Ω
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
f
D
m/n
t
R
t
F
t
D
f
ST
Description
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
25
0.5
0.5
45
Min.
Typ.
48.008
+167
57/17
2
2
55
3
V/ns
V/ns
%
ms
Max.
Unit
MHz
ppm
Z
o
Ω
Note:
9. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
Document #: 38-07162 Rev. **
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