W167B
| Model | W167B |
| Description | 133-MHz Spread Spectrum FTG for Pentium II Platforms |
| PDF file | Total 18 pages (File size: 182K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
Overview
The W167B, a motherboard clock synthesizer, provides 2.5V
CPU clock outputs for advanced CPU and a CPU-divide-by-2
reference frequency for Direct Rambus Clock Generator (such
as Cypress W134) interface. Fixed output frequencies are pro-
vided for other system functions.
I/O Pin Operation
Pins 7, 8, 27, and 28 are dual-purpose l/O pins. Upon power-
up these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of these pins is latched and the pins then become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
each l/O pin and ground or V
DD3
. Connection to ground sets a
latch to “0”, connection to V
DD3
sets a latch to “1”.
Figure 1
and
Figure 2
show two suggested methods for strapping resistor
connection.
Upon W167B power up, the first 2 ms of operation is used for
input logic selection. During this period, these dual-purpose
I/O pins are three-stated, allowing the output strapping resistor
W167B
on each l/O pin to pull the pin and its associated capacitive
clock load to either a logic HIGH or LOW state. At the end of
the 2-ms period, the established logic 0 or 1 condition of each
l/O pin is then latched. Next, the output buffers are enabled,
converting the l/O pins into operating clock outputs. The 2-ms
timer starts when V
DD
reaches 2.0V. The input bits can only
be reset by turning V
DD
off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock outputs is <40Ω (nominal) which is minimally
affected by the 10-kΩ strap to ground or V
DD
. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length to
prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, target (normal) output frequency is delivered assuming
that V
DD
has stabilized. If V
DD
has not yet reached full value,
output frequency initially may be below target but will increase
to target once V
DD
voltage has stabilized. In either case, a
short output clock cycle may be produced from the CPU clock
outputs when the outputs are enabled.
V
DD
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
10 kΩ
(Load Option 1)
W167B
Output
Buffer
Power-on
Reset
Timer
Output Three-state
Hold
Output
Low
D
10 kΩ
(Load Option 0)
Q
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
V
DD
10 kΩ
W167B
Output
Buffer
Power-on
Reset
Timer
Output Three-state
Hold
Output
Low
D
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
Q
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
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